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8-bit d/a converter supporting with i 2 c bus description the CXA1315M/p is developed as a 5-channel 8- bit d/a converter supporting with i 2 c bus. features serial control through i 2 c bus 5-channel 8-bit d/a converter built-in 4general-purpose i/o ports (digital i/o) i/o can be specified to respective ports independently selection of 8 slave addresses possible through address select pins (3 pins) applications the ic, which cannot support i 2 c bus, can support it by connecting its control pin to the CXA1315M/p. structure bipolar silicon monolithic lc absolute maximum ratings (ta = 25?) supply voltage v cc 12 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 960 mw operating conditions supply voltage v cc 8.2 to 9.8 v operating temperature topr ?0 to +75 ? ?1 e88z45e26-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. purchase of sony's i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defind by philips. CXA1315M/p CXA1315M 16 pin sop (plastic) cxa1315p 16 pin dip (plastic)
?2 CXA1315M/p pin configuration (top view) block diagram 16 v cc 1 sw1 15 scl 2 sw0 14 sda 3 dac4 13 sad2 4 dac3 12 sad1 5 dac2 11 sad0 6 dac1 10 sw3 7 dac0 9 sw2 8 gnd sw i/o dac output sw i/o slave address select pin i 2 c bus i 2 c decoder level conversion latch level conversion sw0 to 3 open collector sad2 sad1 sad0 level conversion i 2 c bus sda scl power on reset latch dac amp dac4 latch dac amp dac3 latch dac amp dac2 latch dac amp dac1 latch dac amp dac0 v cc reg v cc gnd
3 CXA1315M/p pin description no. symbol 1 2 9 10 sw1 sw0 sw2 sw3 14 sda equivalent circuit description i/o pin for genera-purpose i/o port v ilmax : 1.5v v ihmin :3v v olmax : 0.4v sda i/o pin for i 2 c bus 150 v cc 4.5k v cc 11 12 13 sad0 sad1 sad2 15 16 scl v cc slave address input pin input at positive logic v ilmax : 1.5v v ihmin :3v scl input pin for i 2 c bus power supply pin 150 v cc 4.5k v cc 3 4 5 6 7 dac4 dac3 dac2 dac1 dac0 8 gnd d/a converter output pin gnd pin 56 v cc v cc 20k 20k 22k electrical characteristics (ta = 25 c, v cc = 9v) no. 1 item circuit current symbol lcc test conditions min. dac 0 to 4 = 127 test circuit 1 8 typ. 11 max. 15 unit ma d/a converter block 2 3 4 5 6 7 differential linearity minimum output voltage maximum output voltage output current output impedance repple rejection dle vmin vmax iout zo grip v (dac0 to 4 = n + 1) v (dac0 to 4 = n) 128 1 v (dac0 to 4 = 191) v (dac0 to 4 = 63) n = 0 to 127 dac 0 to 4 = 0 dac 0 to 4 = 255 current that can be flowed from pins 3 to 7 v ( 1ma) v (1ma) dac 0 to 4 = 127, 2ma dac 0 to 4 = 127, ref = 0 superimose 100hz to v cc , 1vp-p 1 1 1 2 2 3 1 0.1 8.3 1 0 0 0.4 8.5 3 60 +1.1 0.62 8.9 +1 6 40 lsb v v ma ? db
CXA1315M/p sw, sad pins 8 8 9 10 11 low level input voitage high level input voltage low level input current high level input current low level input voltage v il v ih i il i ih v ol input voltage where st0 to st3 become "0" input voltage where st0 to st3 become "1" lnput current when 0.4v is applied lnput current when 4.5v is applied sw 0 to 3 = 1, output voltage when 1ma flows in 4 4 4 4 5 3.0 10 10 0 0 0 0.2 1.5 +10 +10 0.4 v v a a v no. item symbol test conditions min. test circuit typ. max. unit i 2 c bus block items (sda, scl) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ih v il i ih i il v ol i ol c i f scl t buf t hd; sta t low t high t su; sta t hd; dat t su; dat t r t f t su; sto 3.0 0 0 3 0 4.7 4.0 4.7 4.0 4.7 5 250 4.7 5.0 1.5 10 10 0.4 10 100 1 300 v v a a v ma pf khz s s s s s s ns s ns s no. item symbol min. typ. max. unit high level input voltage low level input voltage high level input current low level input current low level output voltage, at 3ma flow to sda (pin 14) maximum flowing current lnput capacitance maximum clock frequency data change minimum waiting time data transfer start minimum waiting time low level clock pulse width high level clock pulse width minimum start preparation waiting time minimum data hold time minimum data preparation time rise time fall time minimum stop preparation waiting time i 2 c bus load conditions: pull-up resistance 4k ? (connected to +5v) load capacitance 200pf (connected to gnd) i 2 c bus control signal t low t buf t hd; sta t r t hd; dat t high t su; dat t f t hd; sta t su; sta t su; sto sda scl ps sr p 4
5 CXA1315M/p electrical characteristics measurement circuit measurement circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 CXA1315M/p i 2 c bus 5v 0.022 10 +9v 100p 100p 100p 100p 100p measurement circuit 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 CXA1315M/p i 2 c bus 0.022 10 +9v 100p 100p 100p 100p 100p 1ma measurement circuit 3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 CXA1315M/p i 2 c bus 0.022 10 +9v 100p 100p 100p 100p 100p 100hz, 1vp-p measurement circuit 4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 CXA1315M/p i 2 c bus 0.022 10 +9v v 4 v 4 = 1.5v (no.8) 2.0v (no.9) 0.4v (no.10) 4.5v (no.11) measurement circuit 5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 CXA1315M/p i 2 c bus 0.022 10 +9v 1ma
6 CXA1315M/p definition of i 2 c bus register 0 1 0 0 sad2 sad1 sad0 r/w msb lsb r/w 0: slave receiver 1: slave transmitter sad0 to 2:11 to13 pin 0: "low" 1: "high" with the lc reset all registers are reset to "0" ? : not defined x: don't care sub address is auto incremented lt can be used as a 6-bit d/a converter by setting the lower two bits of dac0 to 4 registers to "0", but take care that the max. voltage of da output will lower about 100mv compared with the use of 8 bits. control register sub address xxxxx000 xxxxx001 xxxxx010 xxxxx011 xxxxx100 xxxxx101 bit 7 ref dac0 (8) dac1 (8) dac2 (8) dac3 (8) dac4 (8) bit 6 ? bit 5 ? bit 4 ? bit 3 sw3 bit 2 sw2 bit 1 sw1 bit 0 sw0 bit 7 ponres bit 6 0 bit 5 0 bit 4 0 bit 3 st3 bit 2 st2 bit 1 st1 bit 0 st0 status register
7 CXA1315M/p in brackets ( ) number of bits ref (1) : switches d/a converter reference voltage 0: standardizes the inner regulator 1: standardizes voltage resistance divided from vcc sw0 to 3 (1) : selects on/off of pins 1, 2, 9 and 10 (each pin is the open collector output of npn transistor) 0: off 1: on dac0 to 4 (8) : digital data input register of d/a converter 0: output voltage turns to minimum 255: output voitage turns to maximum ponres (1) : detects power on reset 0: master passes from the bus and is reset to "0" after having read this status 1: sets to "1" when power supply is turned on or when there has been a power dip st0 to 3 (1) : detects and registers the voltage condition of pins 1, 2, 9 and 10 0: 1.5v and below 1: 3.0v and above note) sw0 to 3 effective during "0" i 2 c bus signal there are 2 signals in i 2 c bus. sda (serial data) and scl (serial clock). sda is double-way. as sda is bidirectional it has 3 state outputs, h, l and hi-z. i 2 c transfer begins with start condition and ends with stop condition. sda scl start condition s stop condition p h l hi-z l
8 CXA1315M/p i 2 c data write (write from i 2 c controller to ic) i 2 c data read (read from ic to i 2 c controller) sda scl msb 123456 msb lsb hi-z hi-z at "l" during write 7891 89 address ack sub address ack s lsb hi-z msb hi-z 18 9 1 8 9 data (n) data (n + 1) ack ack data (n + 2) hi-z hi-z 8 9 1 8 9 data data ack ack p ? the number of data that can be transferred at a time is confined to units of 8-bit that can be set as required. sub address is incremented automatically. 8 9 1 7 8 9 6 7 1 hi-z address data ack ack p s sda scl at "h" during read read timing 7 8 9 5 6 3 4 1 2 9 lsb msb data ack ack scl read timing ic output sda ? data read is performed with scl rise.
9 CXA1315M/p application circuit 2sc2785 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 CXA1315M/p i 2 c bus 0.022 10 +9v d/a converter output 10k 10k 10k 10k 2sc2785 10k 10k 10k 10k general-purpose output port general-purpose input port slave address for 4ch and 4dh application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same . characteristics diagram 25 0.1 d/a converter output temperture characteristics (ref: 1) t [ c] voltage variation at. 25 c [v] 0255075 0 0.1 data: 0 data: 128 data: 255 data: 255 data: 128 data: 0 v cc = 9v 25 0.1 d/a converter output temperture characteristics (ref: 0) t [ c] voltage variation at. 25 c [v] 0255075 0 0.1 data: 0 data: 128 data: 255 data: 255 data: 128 data: 0 v cc = 9v
10 CXA1315M/p package outline unit: mm CXA1315M package structure package material lead treatment lead material package mass sony code eiaj code jedec code sop-16p-l01 sop016-p-0300 copper alloy solder plating epoxy resin 16pin sop (plastic) 9.9 0.1 + 0.4 16 9 18 1.27 0.45 0.1 5.3 0.1 + 0.3 7.9 0.4 6.9 1.85 0.15 + 0.4 0.5 0.2 0.2 0.05 + 0.1 0.1 0.05 + 0.2 0.2g 0.15 m 0.24 lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. package structure package material lead treatment lead material package mass sony code eiaj code jedec code sop-16p-l01 sop016-p-0300 copper alloy solder plating epoxy resin 16pin sop (plastic) 9.9 0.1 + 0.4 16 9 18 1.27 0.45 0.1 5.3 0.1 + 0.3 7.9 0.4 6.9 1.85 0.15 + 0.4 0.5 0.2 0.2 0.05 + 0.1 0.1 0.05 + 0.2 0.2g 0.15 m 0.24
CXA1315M/p 11 cxa1315p package structure package material lead treatment lead material package mass epoxy resin solder plating copper alloy 19.2 0.1 + 0.4 9 18 2.54 0.5 0.1 1.2 0.15 3.0 min 0.5 min 3.7 0.1 + 0.4 6.4 0.1 + 0.3 7.62 0.25 0.05 + 0.1 0 ? to 15 ? 16 16pin dip (plastic) 1.0 g sony code eiaj code jedec code dip-16p-01 dip016-p-0300 similar to mo-001-ae 1.all mat surface type. two kinds of package surface: 2.all mirror surface type. lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. package outline unit: mm package structure package material lead treatment lead material package mass epoxy resin solder plating copper alloy 19.2 0.1 + 0.4 9 18 2.54 0.5 0.1 1.2 0.15 3.0 min 0.5 min 3.7 0.1 + 0.4 6.4 0.1 + 0.3 7.62 0.25 0.05 + 0.1 0 ? to 15 ? 16 16pin dip (plastic) 1.0 g sony code eiaj code jedec code dip-16p-01 dip016-p-0300 similar to mo-001-ae 1.all mat surface type. two kinds of package surface: 2.all mirror surface type.
12 CXA1315M/p sony corporation cxa1315p package outline unit: mm sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin solder plating copper dip-16p-191 dip016-p-0300-au ms-001-aa 16pin dip (plastic) 300mil 0 ? to 10 ? 0.28 0.06 6.35 0.127 7.62 1 8 9 16 19.35 0.5 2.54 0.254 0.457 0.076 1.016 3.1 min 0.508 min 5.08 max + 0.1 1.0g

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